Controlling on-screen displays

ABSTRACT

An apparatus for controlling synchronization of on-screen display information in an auto-search mode of a radio-frequency receiver ( 2 ) connected to scan an incoming signal for valid channel frequencies, includes a picture intermediate frequency phase-locked loop detector ( 17 ) for supplying an output signal indicating whether an intermediate frequency demodulator is in an unlocked mode which is the case if the incoming signal frequency does not correspond to a valid channel frequency, or in a locked mode, which is the case if the incoming signal frequency does correspond to a valid channel frequency, a video detector ( 18 ) for detecting a video property in the incoming signal, a synchronization phase control loop ( 6, 8, 10 ) which is closed if the video property is detected and the output signal indicates the locked mode, a memory for storing the frequency of the incoming signal as a valid channel when the phase control loop ( 6, 8, 10 ) is closed, and a horizontal oscillator ( 8 ) connected to free run when the phase control loop ( 6, 8, 10 ) is open. This stabilizes an on-screen display even when no signal is present or a weak signal is present.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to on-screen displays, particularly suchdisplays as are commonly used on the picture screen when a televisiontuner is in the auto-search mode.

2. Description of the Related Art

An On-screen display (OSD) typically comprises alphanumeric and/orpicture characters to provide information to the user, for example,regarding channel number, programming choices, and prompting statements.Typically, the OSD signals are supplied to the luminance/chrominanceprocessing part of the television receiver to be displayed on the screensuperimposed on any picture signal received by the tuner. To ensure thatthe OSD always appears in the same position on the screen, it issynchronized with the horizontal and vertical deflection timing pulseswhich are separated in the receiver from the received television signal.

A problem arises when an OSD is required at a time when no picturesignal is being received, for example, during tuning, or if the picturesignal is weak. Then either no timing pulses are present or the timingpulses are very noisy because of residual harmonics which appear asfalse video synchronizing signals at the output of the pictureintermediate frequency demodulator (further referred to as “PIFdemodulator”) which demodulates the intermediate frequency supplied by atuner into a baseband video signal. This tends to produce disturbancesand distortion in the OSD, including jagged edges and vertical bouncebecause the position of the OSD characters will tend to vary from lineto line and from field to field. This is evidently undesirable. Theproblem is particularly acute during an auto search tuning mode of atelevision receiver.

It has been proposed to use a substitute synchronizing signal incircumstances when no suitable external signal is being received. Thisincreases the cost of the receiver. Alternatively, U.S. Pat. No.4,677,484 proposes a dedicated deflection signal source and controlmeans to switch the source from an operating mode, in which it issynchronized with a received synchronizing signal, to a mode in which itis free running, when the incoming signal is determined to have aninvalid or unsuitable synchronizing signal. This again requiresexpensive additional circuitry.

SUMMARY OF THE INVENTION

It is an object of the invention to provide an on-screen display whichobviates the above-mentioned problems. This object is achieved in anapparatus for controlling synchronization of on-screen displayinformation in an auto-search mode of a radio-frequency receiverconnected to scan an incoming signal for valid channel frequencies, theapparatus comprising a detector for supplying an output signalindicating whether an intermediate frequency demodulator is in anunlocked mode, which is the case if the incoming signal frequency doesnot correspond to a valid channel frequency, or in a locked mode, whichis the case if the incoming signal frequency does correspond to a validchannel frequency; a video detector for detecting a video property inthe incoming signal; a synchronization phase control loop which isclosed if the video property is detected and the output signal indicatesthe locked mode; a memory for storing the frequency of the incomingsignal as a valid channel frequency when the synchronization phasecontrol loop is closed; and a horizontal oscillator connected to freerun when the synchronization phase control loop is open.

There is preferably also a coincidence detector to verify thecoincidence detection status to confirm the presence of a valid channelfrequency indicating a real transmission.

According to a preferred embodiment, the video property is a linefrequency signal and the memory may be non-volatile.

According to a second aspect of the present invention, a method isprovided for controlling synchronization of on-screen displayinformation in the auto-search mode of a radio-frequency receiverconnected to scan an incoming signal for valid channel frequencies, themethod comprising the steps of:

(a) initiating a channel frequency search mode;

(b) opening a synchronization phase control loop and setting ahorizontal

oscillator to free run, for example, by switching a vertical divider inthe auto mode;

(c) generating on-screen display information, preferably for a fullscreen;

(d) scanning an incoming signal for valid channel frequencies;

(e) monitoring the incoming signal for the presence of a video property;

(f) if the video property is detected, causing the program to wait onlyfor a predetermined time; if the video property is not detected proceedto step (j);

(g) checking the lock status of the PIF phase-locked loop;

(h) closing the synchronization phase control loop only if the PIF phaselocked loop is locked (or more general, if the PIF demodulator does notcomprise a phase locked loop, when a detector coupled to the PIFdemodulator detects a locked state indicating that it is very likelythat a valid channel frequency is detected;(i) then storing the data if the PIF phase locked loop is locked and thevideo property is present;(j) seeking the next channel and proceeding with step b) as long as notall channels have been searched.

The channel frequency data is preferably stored in a non-volatilememory, and the video property is preferably a line frequency signal.

The accuracy of detecting a channel can be further improved by checkingthe output of a coincidence detector coupled to the phase control loop.In this embodiment the coincidence detector outputs a logical true orfalse signal, depending on whether or not the synchronization phasecontrol loop, while being closed, is synchronizing the horizontaloscillator with the incoming RF signal. If the output is “true”, a validchannel frequency is detected and is stored in a non-volatile memory. If“false”, there is not detected a valid channel frequency, so thisfrequency is not stored.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects of the invention will be apparent from andelucidated with reference to the accompanying drawings, in which:

FIG. 1 is a schematic block diagram illustrating a prior art apparatusand method of synchronizing on-screen displays;

FIG. 2 is a timing sequence diagram for the signal flow chart of FIG. 1;

FIG. 3 is a schematic block diagram illustrating an apparatus and amethod according to the present invention;

FIG. 4 is a timing sequence diagram for the signal flow chart of FIG. 3;and

FIG. 5 is a flowchart illustrating one software implementation of theinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In FIG. 1, a schematic block diagram of a known apparatus is shown inwhich an incoming radio frequency (RF) signal is received by an aerial 1and passed to a television tuner 2. In known manner, the RF signalpasses through a picture intermediate frequency phase-locked loopdemodulator circuit (PIF PLL) 3 which demodulates the received signal toseparate it into the constituent video signal and synchronizing signal.The video signal is passed to a video processor 4 and the synchronizingsignal is applied to a synchronizing signal separator 5. The separator 5may divide the horizontal synchronizing signal H.sync from the verticalsynchronizing signal V.sync. The horizontal signal H.sync is applied toa first phase detector 6 and to a coincidence detection circuit 7, againin known manner. The output of the first phase detector 6 is filteredvia a low-pass filter 9 and fed to a horizontal oscillator 8 which, inturn, supplies horizontal timing circuitry 10, to provide a horizontaldisplay timing signal 11, a second phase reference signal (PH2 Ref), anda Burst-key signal BK.

The vertical signal V.sync is output to a vertical divider 12 andsubsequently to a sandcastle generator 13, which also receives theBurst-key signal BK from the horizontal timing circuitry 10.

A second phase detection circuitry 14 receives the second phasereference signal PH2 Ref and the output signal from the sandcastlegenerator 13, which also provides the horizontal fly-back pulse. Theoutput of the second phase detection circuitry 14 is filtered via asecond low-pass filter 15 and coupled to the horizontal drive circuitry16 which generates a horizontal drive pulse HDP.

FIG. 2 is a timing diagram showing the correspondence between thecoincidence status CS of the coincidence detection circuit 7 and thechannel search status CSS. When the coincidence status CS changes fromzero to one indicating that, while scanning the channel frequencies, achannel has been found, the scanning of channel frequencies is pausedduring a time period Tp (indicated with status “1” in the channel searchstatus CSS diagram). During this pause, the accurate channel frequencyis detected and subsequently stored during storing time Ts in a memory.Thereafter, the channel search status becomes zero again, and thescanning of channel frequencies is resumed until a next channel isfound.

FIG. 3 is a schematic block diagram of an apparatus and a methodaccording to the present invention. All of the known blocks illustratedin FIG. 1 are also present in this diagram, but in addition, extrastages, including a phase-locked loop (PLL) detection circuit 17, a linefrequency detection circuit 18, and a first phase detector controlcircuit 19, are provided as described below.

The PLL detection circuit 17 determines whether the PIF PLL 3 is in alocked state. An output “1” indicates that it is in a locked state,whereas a “0” indicates that it is in an unlocked state.

The line frequency detection circuit 18 determines whether the incomingRF signal received by the aerial 1 has a video property, and thuswhether a valid picture signal is being received. The line frequencydetection circuit 18 detects the line frequency and, if it is present,it is likely that a TV broadcast signal is being received and it is thusdesirable to store information related to this signal in the memory (notshown). Thus, the detection circuit 18 outputs a logic “1”. If the linefrequency is not detected, the detection circuit 18 outputs a logic “0”.The line frequency is actually 15,625 Hz for the European Standards. Theline frequency may have another value which is depending on thebroadcast system (for example, about 31 kHz or 32 kHz for HDTV). Insteadof the line detection circuit 18, also other video property detectioncircuits can be used, indicating the presence of a video signal.

Further logic circuitry in the form of an AND gate 20, assesses theoutputs of the PLL detection circuit 17 and the line detection circuit18 and provides a control signal to the first phase detector controlcircuit 19, accordingly. This control signal can be supplied directly tothe control circuit 19 or via a processor (not shown) which controls theexecution of the method. Also, the function of the AND gate 20 can beperformed by the processor. Specifically, if the PLL is in lock and avideo property is detected, the logic outputs of the detection circuits17 and 18 will both be “1” and as a result a logic “1” is supplied tothe first phase detector control circuit 19 to close the phase controlloop 6, 8, 10 and enable the first phase detector to pass the horizontalsynchronization signal H.sync for synchronization of the OSD displaywith the incoming signal.

On the other hand, if the PLL detection circuit 17 does not indicate a“Lock” or if there is no video property in the incoming signal, a logic“0” is supplied to the first phase detector control circuit 19 to openthe phase control loop 6, 8, 10 and allow the horizontal oscillator 8 tofree-run, thus avoiding interference to the OSD display by poorlyreceived signals.

The switching timing of the following signals can be seen in FIG. 4:

the status signal Ls of the output of the line detection circuit 18,

the status signal PLL-S of the output of the PLL detection circuit 17,

the status signal PC supplied to the first phase detector controlcircuit 19,

the status signal CS of the output of the coincidence detection circuit7, and

the signal indicating the channel search status CSS.

When both status signals LC and PLL-S are “1”, the first phase controlcircuit 19 receives the status signal PC equal to “1”. While status PCequals “1”, the channel search is paused during the time Tp as indicatedwith status “1” of status signal CSS. During this time, the controlcircuit 19 closes the phase locked loop comprising the first phasedetector 6, the horizontal oscillator 8 and horizontal timing 10. Thisallows the coincidence detection circuit 7 to detect whethersynchronization of the horizontal oscillator 8 with the incoming RFsignal has been achieved (indicated with status “1” of status signalCs). If yes, the presence of a channel is confirmed and the channelfrequency is stored during storing time Ts. Thereafter, the next channelis searched (indicated by status “0” of status signal CSS).

FIG. 5 provides a flowchart illustrating the method of the subjectinvention and a software implementation covering the channelinstallation and comprising the following steps:

1. Channel search mode is initiated.

2. The first phase loop 6, 8, 10 is opened (meaning the horizontaloscillator 8 is free-running) and the vertical divider 12 is set in theauto mode.

3. OSD information is generated (preferably for a full screen).

4. The tuner starts to scan the channel frequencies for an incoming RFsignal.

5. The RF signal is checked whether it comprises a line frequencysignal, indicative of a video property.

7. If the line frequency is not detected, the next channel frequency isselected and step 5 repeated until a last channel frequency has beenchecked,

6. If the line frequency signal is detected, the channel frequency iskept constant for a predetermined pause time Tp.

8. The status of the PLL detection circuit 17 is checked

9. If the PLL detection circuit 17 is locked, the first phase detector 6is switched on, (If not, the program proceeds with step 7).

10. The channel frequency is kept constant (allowing the coincidencedetector to reach a final value).

11. The coincidence detection circuit 7 assesses whether the horizontaloscillator 8 is synchronized with the incoming RF signal.

12. If yes, the frequency of the incoming RF signal is stored in anon-volatile memory (NVM) (not shown) and the next channel is selectedin step 7. If no synchronization is detected the method proceedsimmediately to step 7.

13. The program ends when all channels have been scanned.

The IC TDA957X H/N1 is a known TV signal processor which has a closedcaption decoder with an embedded micro-controller. This processor can beapplied to the apparatus and the method of the present invention and,for example, programmed in accordance with the flowchart of FIG. 5 in amanner which will be evident to a skilled person in this field. Itshould be noted that the invention could also be carried into effect byprogramming any one of several similar known processors or othercircuitry and the invention is not intended to be limited to thisillustrated circuit.

The invention is applicable to traditional television receivers and alsoto personal computers equipped with a television function.

It should be noted that the above-mentioned embodiments illustraterather than limit the invention, and that those skilled in the art willbe able to design many alternative embodiments without departing fromthe scope of the appended claims. In the claims, any reference signsplaced between parentheses shall not be construed as limiting the claim.The word “comprising” does not exclude the presence of elements or stepsother than those listed in a claim. The word “a” or “an” preceding anelement does not exclude the presence of a plurality of such elements.The invention can be implemented by means of hardware comprising severaldistinct elements, and by means of a suitably programmed computer. Inthe device claim enumerating several means, several of these means canbe embodied by one and the same item of hardware. The mere fact thatcertain measures are recited in mutually different dependent claims doesnot indicate that a combination of these measures cannot be used toadvantage.

1. An apparatus for controlling synchronization of on-screen displayinformation in an auto-search mode of a radio-frequency receiverconnected to scan an incoming signal for valid channel frequencies, theapparatus comprising: a detector for supplying an output signalindicating whether an intermediate frequency demodulator is in anunlocked mode, which is the case if the incoming signal frequency doesnot correspond to a valid channel frequency, or in a locked mode, whichis the case if the incoming signal frequency does correspond to a validchannel frequency; a video detector for detecting a video property inthe incoming signal; a synchronization phase control loop which isclosed if the video property is detected and the output signal indicatesthe locked mode; a memory for storing the frequency of the incomingsignal as a valid channel frequency when the synchronization phasecontrol loop is closed; and a horizontal oscillator connected to freerun when the synchronization phase control loop is open.
 2. Theapparatus as claimed in claim 1, wherein the video property to bedetected comprises a line frequency signal.
 3. The apparatus as claimedin claim 1, wherein said apparatus further comprises: a coincidencedetection circuit for verifying a coincidence detection status toconfirm the presence of a valid channel frequency, the memory storingthe frequency if the coincidence detection circuit confirms the presenceof a valid channel.
 4. A method of controlling synchronization ofon-screen display information in the auto-search mode of aradio-frequency receiver, the method comprising the step of: (a)initiating a channel frequency search mode; (b) opening asynchronization phase control loop and setting a horizontal oscillatorto a free running mode; (c) generating on-screen display information;(d) scanning an incoming signal for valid channel frequencies; (e)closing the phase control loop and pausing the scanning for apredetermined time if the incoming signal comprises a video property andan intermediate frequency phase-locked loop is locked; (f) storingchannel data while the phase control loop is closed; (g) scanning forthe next channel.
 5. The method as claimed in claim 4, wherein the videoproperty to be detected is a line synchronizing signal.
 6. A TV signalprocessor comprising means for carrying out the method of claim
 4. 7. Atelevision apparatus comprising the apparatus of claim 1 and a displaydevice for displaying the on-screen display information.